HDL Logic Simulation

Introduction to the syntax and elements of the basic Verilog language such as modules and ports; hierarchical modeling; gate-level modeling; dataflow modeling; switch-level modeling; tasks and functions; timing and delays; user-defined primitives; synthesizing and implementing designs. Emphasis is on the simulation and test-bench aspects. This course is dually listed with an equivalent graduate-level course (EE 543) and requires a minimum GPA of 2.75 or the instructor's permission for admission.